Sigma-delta modulators are widely used in consumer audio and precision measurement devices, such as 24-bit audio analog-to-digital converters (ADC). Signal processing is performed in the digital domain rather than in the analog domain, allowing for power savings and performance improvements as semiconductor processes improve. The sigma-delta modulator samples the input signal at a much higher frequency and spreads noise over a wider frequency band. Such over-sampling and noise shaping can provide higher levels of linearity and dynamic range.
Chopper stabilization is sometimes used to shift the noise to a higher frequency, and then to remove the noise after amplification. One multiplier is inserted before the input of the first-stage amplifier, while a second multiplier is inserted at the output of the first-stage amplifier. The multipliers are controlled by a chopping clock. The input signal is shifted to odd harmonics of the chopping clock by the first multiplier. Unwanted noise at the amplifier input remains at a low frequency. After the noise and harmonics are amplified, the second multiplier shifts the signal from the odd harmonics back to the lower frequency band, and at the same time shifts the amplified low-frequency noise up to the harmonics where it can be filtered out. The signal at the lower frequency band is thus removed of the unwanted noise.
FIG. 1 is a diagram of a chopper-stabilized sigma-delta modulator. FIG. 1 represents a block diagram of a system desired by the inventors, rather than representing any prior art per se. A differential input signal VINP, VINN represents an analog signal and is input to sample, hold, and integrate block 120. Non-overlapping phase clocks P1, P2 control switches within sample, hold, and integrate block 120 to connect the analog input VINP, VINN to sampling capacitors during P1, and to disconnect the analog input and apply feedback to the sampling capacitors during P2. The sampling capacitors drive the output of sample, hold, and integrate block 120 during P2 but are isolated from the output during P1. P1 is the sample phase while P2 is the integrate phase.
First-stage amplifier 140 is stabilized by the addition of input chopper 132 and output chopper 134. Choppers 132, 134 swap the differential signals when chopper clock C2 is active, but pass through the differential signals when C1 is active. Chopper clocks C1, C2 are non-overlapping and operate at a lower frequency than phase clocks P1, P2.
Integrating capacitors (not shown) may be added around input chopper 132, first-stage amplifier 140, and output chopper 134. A second stage of sample, hold, and integrate block 122 and second-stage amplifier 142 operate in a similar way, but without choppers around second-stage amplifier 142. Quantizer 14 is a 1-bit quantizer, differentiator, delta function, comparator, or single-bit digital-to-analog converter (DAC) that generates differential output OUTP, OUTN, which are also fed back to sample, hold, and integrate blocks 120, 122.
For better linearity in a high-resolution sigma-delta modulator ADC, switches in sample, hold, and integrate block 120 may need a larger on-resistance Ron. A larger Ron is achieved by using slightly larger transistors for the switches. However, these larger transistors also have a larger capacitance and thus have more charge under their channels when turned on. When the transistor switches turn off, some of this charge is pushed to the source and the drain nodes. The larger Ron requires a larger gate size and thus more charge is pushed to the source and drain nodes.
Injected charges 150 are such unwanted charges that are pushed to the source and drain nodes when transistor switches within sample, hold, and integrate block 120 are switched off, such as at the end of P1 or P2. These injected charges 150 pass through input chopper 132 producing voltage spikes on the inputs of first-stage amplifier 140. These voltage spikes are then amplified by first-stage amplifier 140, resulting in error-producing offsets that can feed back and propagate through second-stage amplifier 142 to the outputs.
Injected charges 150 may be injected just before chopper clocks C1, C2 switch, causing errors in chopper stabilization. Spurs may be added to the signal band when charge injection occurs at a critical time just before chopper clocks switch.
FIG. 2 shows a traditional chopper clock timing that causes voltage spikes as P2 clocks are turned off just before chopper clocks are switched. Phase clocks P1, P2 are non-overlapping and control sampling and integration in sample, hold, and integrate block 120 (FIG. 1). Chopper clocks C1, C2 are also non-overlapping but operate at a divided-down frequency, such as one-half or one-fourth the frequency of phase clocks P1, P2.
In the traditional timing, P2 falling causes chopper clock C2 to fall. P1 rising causes C1 to rise after some propagation delay. Voltage spikes 152 occur on the transistor switches in sample, hold, and integrate block 120 as P2 falls. These voltage spikes 152 occur after P2 falls, but before C2 falls, when C2 is still active. Thus the injected charge is passed through the transistors that are open during C2 in input chopper 132. Additional charge (not shown) is then injected on these same nodes as C2 falls. Thus voltage spikes 152 are modulated and demodulated by input chopper 132 and output chopper 134, resulting in errors that are not cancelled out.
FIG. 3 shows another prior-art chopper clock timing that causes voltage spikes as P1 clocks are turned off just before chopper clocks are switched. See for example U.S. Pub. No. 2010/0289682 by Groeneold, FIG. 4.
In this prior-art timing, P1 falling causes chopper clock C2 to fall. Then the other chopper clock C1 rises. Finally P2 rises. Chopper clocks C1, C2 change during non-active periods when both P1 and P2 are low.
Voltage spikes 154 occur on the transistor switches in sample, hold, and integrate block 120 as P1 falls. These voltage spikes 154 occur after P1 falls, but before C2 falls, when C2 is still active. Thus the injected charge is passed through the transistors that are open during C2 in input chopper 132. Voltage spikes 154 are modulated and demodulated by input chopper 132 and output chopper 134, resulting in errors that are not cancelled out. Also, additional charge (not shown) is then injected on the outputs by transistors in output chopper 134 as C2 falls.
In both FIG. 2 and FIG. 3, voltage spikes occur when the leading phase clock falls, as charge is injected by the transistor switches closing. These voltage spikes occur at a critical time just before the chopper clocks switch. Thus the voltage spikes are modulated and demodulated along with the input signal at this critical time.
What is desired is a sigma-delta modulator with and improved chopper-clock timing. A switched-capacitor integrator sigma-delta modulator is desired than does not inject charge just before chopper clocks toggle. A sigma-delta modulator with improved linearity and noise margins is desired.